DRAM simulator for design and analysis of digital systems

The DRAM is a typical bottleneck of a digital system. Moreover, the architectures are getting more complex, which makes their evaluation harder. In this paper, we propose a fast and early estimation of the memory system performance with an actual application in mind. A DRAM simulator, Rascas, developed for this purpose is presented. Rascas is used to study the DRAM behavior with several memory system con®gurations. The results show that the bandwidth of the same DRAM arrangement can vary over 50% with typical cache con®gurations and applications. We also show that the packet-oriented multi-bank architectures can exploit the temporal locality of the memory references better than the traditional architectures.